The present invention relates to the field of semiconductor device manufacturing, and more particularly, to the process of providing interconnection structures that interconnect integrated circuits in semiconductor devices.
In very and ultra large scale integration (VLSI and ULSI) circuits, insulating or dielectric material, such as silicon dioxide, of the semiconductor device is patterned with several thousand openings for the conductive lines and vias which are filled with conductive material, such as metal, and serve to interconnect the active and/or passive elements of the integrated circuit. The interconnection process is used for forming the multi-level signal lines of metal, such as a copper, in an insulating layer, such as polyimide, of a multi-layer substrate in which the semiconductor devices are mounted.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings are also formed. In the standard dual damascene process, the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via openings and the pattern is anisotropically etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with a resist material which is exposed to a second mask with the image pattern of the conductive lines in alignment with the via openings. During anisotropic etching of the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and the grooves are filled with metal. The excess metal was removed by CMP (chemical mechanical polishing) techniques. One of the advantages of dual damascene processing is that it permits the filling of both the conductive grooves and the vias with metal at the same time, thereby eliminating process steps. Furthermore, with single damascene, since two different metal deposition steps were used, an interface exists between the conductive via and the conductive wiring.
One dual damascene method described in U.S. Pat. No. 5,705,430 uses a sacrificial via fill. In this method, a first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is disposed on the first layer. Using a conductive line pattern, aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings. The sacrificial material is not etchable by the etchant performing the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which a first insulating layer is resistive or less selective. Conductive material is then deposited in the conductive line and the via openings.
U.S. Pat. No. 5,635,423 describes a simplified dual damascene process for multilevel metallization and interconnection structure. An opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and the first insulative layer. The trench and the via are then simultaneously filled with conductive material. Alternatively, the via is defined on the etch-stop layer. The resist layer is then deposited and masked for the trenches. The large opening for the trench and the smaller opening for the via are simultaneously etched. The trench and the via are then simultaneously filled with conductive material.
Although both of the above described processes provide the desired dual damascene structure, there is a continuing goal of simplifying the process even further and thereby making it less expensive.
There is a need for a dual damascene process that is less complicated than known dual damascene processes, yet still attains the desired dual damascene structure without an interface between the via and the conductive wiring. There is also a need for a method of producing a metal structure without using CMP techniques.
These and other means are met by embodiments of the present invention which provide a method of forming a conductive wiring and a via in which a via opening is formed in a first insulating layer. A conductive wiring mask layer is deposited and patterned over the first insulating layer so that an opening in the conductive wiring mask layer is provided over the via opening. Conductive material is then deposited in the via opening and in the conductive wiring mask layer opening to form the conductive wiring in the via.
Since the conductive wiring mask layer is used in the present invention to receive the deposited conductive material to form the conductive wiring, a separate step of etching of insulating material to form a conductive wiring opening is unnecessary. This greatly reduces the overall etching requirements and costs of manufacture.
In certain embodiments of the invention, the conductive wiring mask layer is removed after the depositing of the conductive material in the via opening and the conductive wire mask layer opening. A second insulating layer, comprising benzocyclobutene (BCB), for example, is deposited over the first insulating layer and the conductive wiring. Hence, certain embodiments of the present invention provide the same dual damascene structure as in the known processes, with a via formed within a first insulating layer, and conductive wiring within a second insulating layer. This is accomplished, however, without etching of the second insulating layer.
The earlier stated needs are also met by other embodiments of the present invention which provide a method of forming a layered conductive structure in a semiconductor device comprising the steps of forming an opening in a first insulating layer and patterning a resist layer on the first insulating layer. A space is defined in the resist layer that is located over the opening. The opening in the first insulating layer and the space in the resist layer are simultaneously filled with conductive material to form the layered conductive structure.
The present invention provides the advantage of forming integral layered structures without etching a second layer. This has significant cost advantages over methods which employ etching of the second layer, while still providing conductive structures that are integrally formed. Hence, the completed layered conductive structure will not have an interface between the conductive material of the first and second layers. This embodiment is not restricted to conductive vias and wiring, but rather may be used to create other forms of layered conductive structures.
The present invention also provides, in certain embodiments, an article comprising a first insulating layer with a conductive structure in the first insulating layer. A photoresist layer is provided over the first insulating layer, with an opening in the photoresist layer that is disposed over the conductive structure. Conductive wiring fills the opening in the photoresist layer and contacts the conductive structure. In conventional articles, conductive structure is provided in a first insulating layer which has been etched, and the conductive wiring that contacts the conductive structure is provided in a second insulating layer that has been likewise etched. The present invention has the advantage of avoiding the etching of the second insulating layer and instead providing a conductive wiring in a photoresist layer. The article of the present invention may be used to provide interconnections by further processing of the article, including removing the photoresist layer and depositing a second insulating layer over the first insulating layer and the conductive wiring.
An advantage of the present invention is that it eliminates the requirement of CMP removal of excess metal during the filling process.
The foregoing and other features, aspects and advantages of the present invention will become apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.